The invention relates generally to a method and apparatus for testing of digital circuits and in particular to a method and apparatus for verifying timing of signals occurring during the simulation and testing of a digital circuit.
The use of computer simulation for verifying the logical operation of a digital circuit is well known In addition, there is often provided a timing analysis to ensure that a design works correctly, not only "logically," but when its detailed timing is taken into account. This analysis attempts to ensure that all component timing constraints will be satisfied during the operation of the design. The constraints can include the setup and hold times for an element and constraints such as the write enable timing to address a storage device such as a random access memory (RAM).
The timing analysis can further ensure that all high level timing specifications for the circuit design, such as the cycle time and timing of input and output signals, operate in accordance with the selected specifications. The analysis diagnoses timing problems which may be present and explain which portions or set of delays in the equipment are responsible for a particular timing problem. In this manner, therefore, the timing analysis aids the designer in finding a solution for a problem and for more quickly testing different strategies for repairing or fixing the problem
The timing analysis also, in combination with the logical analysis, produces more consistent results, regardless of which of a batch of parts is used during manufacture This of course requires that each part be fully specified, including, for example, its minimum, maximum and typical delay times Further, the analysis aids the designer in selecting a cycle time for the circuitry, which, together with design strategies and methods, will result in a fast but correct operation.
The role of the timing analysis generally changes as the design process evolves In its early design stage, the main role of the timing analysis is to allow the designer to learn more about the design in an upper level manner. It will, for example, point out the critical paths and help to select a target cycle time. In addition, different design alternatives can be tested to determine which approach produces the best results In a later design stage, the primary goal is to ensure that the design operates at the selected speed or cycle time. During this phase, timing analysis determines whether the component and system timing specifications will be met during typical operations of the design.
Presently, the two common methods of performing timing verification are the static timing analysis and the dynamic timing analysis. A static timing analysis generally uses critical path analysis and works without pattern stimuli or any real time simulation. The goal of the static timing analysis is to complete a timing verification in a single pass. Since it is designed for only one pass through the circuit, it takes little computer time and can be used effectively only on designs with simple or no clock mechanisms. The results of the analysis, which can typically include a number of false violations, must be verified manually. For a complex design, the user must partition the design into separate sections and apply the static analysis, one section at a time. This is not only time consuming, but also error prone since the process must be enabled manually
A dynamic timing analysis, for "min/max simulation," is a method for performing timing verification in a manner similar to the simulation used to do functional or logical verification. This method is simulation based and requires simulation patterns Like the logic simulation, the number of patterns required to achieve a high level of confidence in the results is large For each input pattern, the circuit will be simulated with a min/max delay. Hence a change on a wire happens with a minimum arrival time and a maximum arrival time The dynamic timing analysis requires substantial computer time to perform the analysis and the result is very dependent on the simulation patterns specified It is almost impossible for a user to specify all reasonable simulation patterns when the computer time costs are taken into account.
Accordingly, one is left with either a relatively simple static approach which requires substantial manual intervention when complex designs are used and wherein substantial numbers of false violations can be obtained or a dynamic timing analysis approach wherein substantial-computer time must be employed for even relatively small numbers of simulation pattern inputs.
It is therefore a primary object of the invention to provide a timing analysis method and apparatus which performs substantially complete timing analysis using all reasonable simulation pattern inputs without requiring excessive computer time, while maintaining the number of false violations to a minimum or none. Other objects of the invention are a method and apparatus which provide, using a few timing patterns, two paths through the circuitry which are the minimum and maximum path times from input node to output node Another object of the invention is for enabling a timing analysis to handle logical circuit loops and logical storage elements such as latches or flip-flops.